FERMAT Tools/Techniques
The following tools and techniques were developed by the fermatians, all of which are open-source. The download point can be reached by following the appropriate links.
Embedded Systems
Tools with advanced features and techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs. These tools/techniques are needed to ensure the quality, reliability, manageability and flexibility of embedded application design and development.
- Heterogeneous and Behavioral Hierarchy Extensions for SystemC
- SystemC Kernel Extensions for Heterogeneous System Modeling A Framework for Multi-MoC Modeling & Simulation
- An Introspective and Service oriented Architecture for Validating System Level Designs in SystemC
- SystemCXML: FERMAT's SystemC Parser
- EWD Metamodeling Environment
- FERMAT's SystemC IDE
System On a Chip
The rapid increase in design complexity has become a serious limiting factor in system-on-a-chip (SoC) designs. To manage the exponential increase in design complexity, efforts must concentrate on developing the required tools and integrating them with the appropriate techniques to offer a higher degree of design automation.
Formal Verification
Computational systems, consumer electronics, avionics and other mission critical systems are dependent on complex hardware and software components. Most often, these systems entail a complexity beyond the scope of ordinary validation techniques. Formal verification and formal methods have been emerging as viable techniques for mitigating this increasing system complexity and the resulting validation challenges. Formal Methods include describing the behaviors of systems mathematically and reasoning about them to prove correctness and analyze their behavior and performance. The key aspects of formal methods include specification, verification, and testing techniques for enhancing the quality of the software and hardware development. It is known from industrial trends that the validation cycle is often the limiting factor for the decrease in time-to-market. Some industry experts estimate that about 70\% of the design cycle is spent on verification.
Nanotechnology
It has been predicted by experts that nanoelectronic devices will be more susceptible to manufacturing defects and transient errors. Fault-tolerant architectures may be possible solutions to mitigate this reliability problem. Usually there are many fault-tolerant schemes that have been proposed in the literature. Hence, designers need to analyze and compare these fault-tolerant techniques to make an informed choice for a specific system.
There are two distinct approaches that can be used to analyze the reliability of structural redundancy based nanoarchitectures. The analytical approach entails complex combinatorial modeling of fault-tolerant architectures, whereas, the other approach is declarative in the sense that instead of forming complex combinatorial arguments for generic architectures, specific architectural configurations, explicit configurations at the primary inputs and specific gate and interconnect failure probability values are used to develop probabilistic models of the systems. We have developed declarative based automation methodologies to compute different system design trade-offs such as reliability-redundancy, reliability-redundancy-performance, etc.
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Recent News
2009-02-05:
Publications Update
An initial commit of the publication display function has been made
2009-02-04:
One Step Closer to Publications
After adding an item to the Fermatian editor allowing the user to select their Aigaion ID, we are now one step closer to having a full list of publications on each Fermatians personal page.
2009-01-27:
Aigaion Update
All backend functionality has bee updated to work with Aiagion.

